1. Field of the Invention
The present invention relates to a logic circuit including logic gate combination circuits and scan flip-flop circuits having a scan path for a test mode, and more particularly, to the improvement of scan flip-flop circuits.
2. Description of the Related Art
In a logic circuit including a large number of logic gates such as AND gates, NAND gates, OR gates, NOR gates, exclusive OR gates and the like, and a large number of flip-flop circuits interposed between the logic gates, the flip-flop circuits cannot usually be accessed directly front the exterior. Therefore, in order to test the logic gates, the logic gates have to be operated step by step, which increases the test time.
In order to reduce the test time for the logic gates included in the logic circuit, a scan path is provided to serially connect the flip-flop circuits to each other between a scan-in terminal and a scan-out terminal. That is, when the scan path is activated, the flip-flop circuits can serve as a shift register. Thus, input data can be written from the scan-in terminal through the scan path into an arbitrary flip-flop circuit, and output data can be read from an arbitrary flip-flop circuit through the scan path to the scan-out terminal.
A prior art scan flip-flop circuit is constructed by a selector circuit operated by a selection signal, a master latch circuit clocked by a clock signal, and a slave latch circuit clocked by the clock signal (see: JP-A-1-96573). This will be explained later in detail.
In the above-described prior art scan flip-flop circuit, however, since there is actually a skew between a clock signal supplied to one scan flip-flop circuit and a clock signal supplied to its adjacent scan flip-flop circuit, a normal operation of the scan flip-flop circuits cannot be guaranteed. This also will be explained later in detail.